Many microdevices, such as integrated circuits, have become so complex that these devices cannot be manually designed. For example, even a simple microprocessor may have millions and millions of transistors that cooperate to form the components of the microprocessor. As a result, electronic design automation tools have been created to assist circuit designers in analyzing a circuit design before it is manufactured. These electronic design automation tools typically will execute one or more electronic design automation (EDA) processes to verify that the circuit design complies with specified requirements, identify problems in the design, modify the circuit design to improve its manufacturability, or some combination thereof. For example, some electronic design automation tools may provide one or more processes for simulating the operation of a circuit manufactured from a circuit design to verify that the design will provides the desired functionality. Still other electronic design automation tools may alternately or additionally provide one or more processes for confirming that a circuit design matches the intended circuit schematic, for identifying portions of a circuit design that do not comply with preferred design conventions, for identifying flaws or other weaknesses the design, or for modifying the circuit design to address any of these issues. Examples of electronic design automation tools include the Calibre® family of software tools available from Mentor Graphics Corporation of Wilsonville, Oreg.
As electronic devices continue to have smaller and smaller features and become more complex, greater sophistication is being demanded from electronic design automation tools. For example, manufacturing technology faces increasing challenges related to yield, reliability, and leakage and timing variability. These challenges have led to a host of design for manufacturability (DFM) techniques because process improvements alone are not sufficient. The early DFM applications addressed yield issues caused by random defects and catastrophic failures. These process-based, or physical, DFM solutions identify and correct design areas that are vulnerable to functional failures, such as shorts and opens. Wire spreading, via doubling, and critical area analysis have become mainstream.
At 65 nm and below, parametric failures become the dominant yield-limiting mechanism. Manufacturing variations affecting power, timing, or other performance specifications cause parametric yield loss. These failure mechanisms are addressed by the next generation of DFM solutions, Electrical DFM (EDFM). EDFM tools address device or interconnect parameters that are affected by process variability and can adversely impact chip performance. Lithography and chemical-mechanical polishing (CMP) modeling, combined with device characterization and timing analysis, capture the effects of process variations on chip performance. Some advanced EDFM methodologies can optimize designs, on a gate-by-gate basis if desired, to reduce variability and improve timing. Electrically-driven optical proximity correction (OPC) tools tweak the manufacturing process itself to implement the optimized solution proposed by an EDFM tool.
A fundamental principle behind all EDFM solutions is that these tools are aware of design characteristics and requirements, such as power and timing, and can use them to estimate the effect of a particular manufacturing process on the design, or to influence the manufacturing process. To do this, EDFM tools should have the ability to analyze logical netlist and physical layout in context.
Most EDFM tools are still limited by the restrictions inherent in a traditional verification flow, which is very compartmentalized. The flow typically includes 1) design rule checking (DRC), layout analysis, and parameter extraction; 2) layout vs. schematic (LVS) and logical analysis (electrical rule checking, or ERC); 3) layout parasitic extraction (LPE); and 4) simulation. At the same time, the design schematic goes through a separate tool chain, only meeting the layout data during the LVS step.
The DRC and physical DFM tools have the most detailed layout information, but almost no understanding of the logical circuit to be implemented by a physical layout. The LVS tool, on the other hand, performs very complex logical analysis, and can be aware of the design intent, but it has only limited information about the physical layout. It is desirable to have an integrated verification platform and corresponding methods for cross-domain design-dependent DFM, or logic-driven verification.